Hardware Implementation of "Supplementary Symmetrical Logic Circuit Structure" Concepts

A test chip was fabricated in a standard 1.2-micron CMOS technology using Supplementary Symmetrical Logic Circuit Structure (SUS-LOC) concepts. The test chip demonstrates several ternary logical functions as well as the flexibility of the SUS-LOC structure. Logic functionality and switching performance of the chip were simulated and verified experimentally. Simulated and experimental results are presented and discussed. 1.0: Introduction After a brief review of the Supplementary Symmetrical Logic Circuit Structure (SUS-LOC) [1-3], we describe and discuss the simulated and experimental performance of a test chip realized in a standard 1.2-micron CMOS technology. 2.0: SUS-LOC Structure The SUS-LOC structure is described in references [1-3] and is therefore not discussed in detail. A few of the features that make the SUS-LOC structure attractive for the ULSI MVL circuits of the 21st Century are: a nominally zero DC power requirement, nano-second switching times, well defined logic level domains, and fabrication can be achieved with inexpensive and available MOS techniques. The output node of SUS-LOC based ‘r’-valued logic circuits is connected to a power supply or ground via pass transistor networks comprised of enhancementand/or depletion-mode, Nand P-channel FETs with multiple application-specific threshold voltages as required by the logic function being realized. For a given input combination only one path conducts from a power supply or ground to the output. Pass-transistor network design procedures are given in the references. 3.0: SUS-LOC CMOS Test Chip Five chips were fabricated using the standard MOSIS [4] 1.2-micron CMOS N-well Tiny Chip technology, packaged in 40 pin DIPs and a microphotograph is shown in figure 1. The MOSIS technology has only single threshold enhancement-mode Nand P-channel FETs. Therefore, depletion-mode FETs and enhancement-mode FETs with application-specific threshold voltages were replaced with circuits that provide equivalent switching characteristics. The use of replacement circuits does not hinder demonstrating the correct operation of SUS-LOC circuits nor the evaluation of their performance. The test chip circuits used minimum transistor dimensions, mask width of 1.8 and length of 1.2-microns, except the replacement circuits which used device sizes designed to produce SUS-LOC switching characteristics. 3.1: Test Chip Overview The component functions of a ternary Half Adder (A+B+Carry) as well as radix converters were selected to demonstrate SUS-LOC circuit operation. 3.2: Test Chip Sub-Circuits The 40-pads of the test chip allowed inclusion of 2 binary-to-ternary converters, 2 Half Sigma gates, 2 Carry-1 gates, and a ternary-to-binary converter. Each cell’s inputs and outputs were brought to pads allowing each cell to be characterized separately. To form the ternary Half Adder shown in figure 2, the cells were externally connected. The ternary logic level voltages are V2=5 volts, V1=2.5 volts, and V0=0 volts, and the binary logic level voltages are V1=5 volts, and V0=0 volts. 3.2.1: Radix Conversion The test chip uses Radix Converting Read Only Memories (RCROM) to perform radix conversion. Figure 3 shows a block diagram of an RCROM which is similar to binary ROMs except for the differential driver/level changers used to ensure proper voltage levels to drive the FETs of the memory array, and maintain a fully active device. 3.2.1.1: Operation of an RCROM The value to be converted from the Source radix (S’r’) to a Destination radix (D’r’) is presented to an RCROM as an address that is decoded to produce Row and Column select signals. The Row and Column selects are connected to the input of a differential driver. The Row driver outputs R0a, R0b through Rna, Rnb control the gates of FETs that form the memory array. The Column driver outputs C0a, C0b through Cna, Cnb control one transmission gate for each place of the output. When a Row becomes active, the FETs of the memory array connected to the active Row driver turn ON connecting a Column line to the supply voltage representing the required D’r’ logic level for that Row and Column combination. When a Column becomes active one transmission gate for each place of the D’r’ output turns ON and connects a Column line to an output node. Thus, an n-place S’r’ value is converted to the equivalent m-place D’r’ value. 3.2.3: Carry Circuit The ternary Half Adder, shown in figure 4, uses two ternary Carry-1 gates. A Carry-1 gate produces an output that is independent of the sum calculation. If the sum of the inputs is greater than two, the output is logic level 1; otherwise, the output is logic level 0. The I/O mapping is labeled “Carry 13" in figure 4. 3.2.4: Half-Sigma Gate Two Half-Sigma gates (SIGMA3) are used in the test chip. The I/O mapping is shown in figure 4 labeled ‘Half Sigma3'. The Half Sigma gate’s A and B inputs are ternary and its carry input (CYI) uses logic 0 and 1. The Half Sigma’s output is the modulo-3 sum of the inputs. 3.3: SUS-LOC CMOS Test Chip Layout The SUS-LOC test chip used the standard MOSIS Tiny Chip 40 pad frame with analog pads. The circuitry was placed in the active area and wired to the pads. The Tiny Chip’s 4 corner VDD and VSS pads were left in place and used to bias the pads. Separate pads were used for the logic level voltages. The arithmetic functions and radix converters were connected off-chip, as shown in the block diagram of figure 2, to form a two-place ternary Half Adder. This direct connection of minimum size FETs to chip pads, and therefore, package pins and test fixtures, will yield very long delay and transition times, as was observed in the test data. In this first SUS-LOC test chip the buffers needed to improve timing performance were not included to prevent obscuring information about the behavior of the pass transistor networks. All circuit layouts were kept straightforward to allow easy debugging. The circuits and layouts were not optimized to any performance figure of merit and used about half of the available active area. 4.0: Simulated Performance HSPICE simulation of each cell was performed and the results are shown in tables A, B, and C. Since there are 2 copies of each ternary cell, the cell outputs are identified with an A or B to indicate the different cells. Table A contains the simulated propagation delay times for the binary-to-ternary converters. Table B shows the simulated propagation delay times for the Carry-1 gates, CyA and CyB, and the Half Sigma gates, A and B. The simulated ternary-to-binary converter propagation delay times are shown in table C.